Semiconductor device geometries have dramatically decreased in size since such devices were first introduced several decades ago. Since then, integrated circuits have generally followed the two year/half-size rule (often called Moore's Law), which means that the number of devices on a chip doubles every two years. Today's fabrication plants are routinely producing devices having 0.35 μm and even 90 nm feature sizes. Fabrication of electronics devices typically entails designing components defined by a multitude of microelectronic circuits. Using fabrication technology, several microcircuits can be integrated on a single chip to form an integrated circuit (“IC”). The chips communicate with each other through a plurality of nodes or I/O (input/output) ports. As the integrated circuits diminish in size, new challenges arise in packaging the integrated circuit into an electronic device.
Conventionally, microprocessors formed on different semiconductors communicate through their respective I/O pins and through traces formed on a PCB. The traces span the gap between the microprocessors, enabling parallel communication between connected processors. The PCB traces create additional processing steps and quality concerns for the manufacturer. For example, efficient quality control is required to ensure precise placement of the PCB traces between the appropriate chips. Also, the design architecture of the PCB trace has to be optimize in order to avoid current leakage and other physical losses. Finally, since the traces are very thin electrical connections, they can be easily disconnected causing failure of the finished device.
Accordingly, there is a need for an inter-chip communication method that overcomes these and other disadvantages of the prior art.